1. Field of the Invention
The present invention relates to a synchronization circuit, a synchronization method, and a reception system.
More particularly, the invention relates to a synchronization circuit, a synchronization method, and a reception system for enabling an appropriate loop gain to be established in keeping with the individual differences and time jitters characteristic of a particular receiver.
2. Description of the Related Art
Recent years have witnessed phenomenal advances in wireless digital transmission technologies for mobile phone communications, satellite or terrestrial digital broadcasts, and wireless LAN (local area network) communications. With wireless digital transmission systems, it is vitally important to establish stable synchronization with carrier waves and to maintain synchronization with phase and frequency fluctuations subsequent to the establishment of synchronism in order to attain high transmission quality.
To establish and maintain synchronization requires a synchronization circuit which detects highly accurately the differences in phase and frequency between a local oscillator signal generated by a local oscillator of the receiver on the one hand and a signal received thereby on the other hand and which corrects the phase and frequency of the received signal in such a manner as to reduce these differences. PLL (phase-locked loop) circuits are often used as the typical synchronization circuit that establishes synchronization in phase and frequency with the received signal.
FIG. 1 is a schematic view showing a partial structure of an ordinary receiver that includes a frequency/phase synchronization circuit using a digital PLL. As shown in FIG. 1, the receiver includes a radio frequency (RF) circuit 2 and a demodulation circuit 3. A received signal acquired by an antenna 1 having received radio waves is input to a multiplier 2-1 of the RF circuit 2.
The multiplier 2-1 multiplies a local oscillator signal fed from a local oscillator 2-2 by the received signal coming from the antenna 1. The signal resulting from the multiplication is forwarded from the multiplier 2-1 to a low-pass filter (LPF) 2-3.
The local oscillator 2-2 generates the local oscillator signal and sends it to the multiplier 2-1. The LPF 2-3 admits the multiplication signal coming from the multiplier 2-1, and performs a filtering process on the input signal to let pass only the low-frequency component. The filtered signal is output to an A/D (analog/digital) converter 2-4.
It is assumed that fc stands for the frequency of the received signal having undergone modulation such as PSK (phase shift keying) modulation, θc for the phase of the received signal; f0 for the frequency of the local oscillator signal generated by the local oscillator 2-2, and θ0 for the phase of the local oscillator signal. The signal output by the LPF 2-3 includes a frequency difference Δf corresponding to fc-f0 and a phase difference θ corresponding to θc-θ0.
The A/D converter 2-4 performs analog-to-digital conversion of the signal output from the LPF 2-3. The A/D conversion provides a digital received signal ri that is fed to the demodulation circuit 3. Reference character “i” denotes the ordinal position of the symbol represented by the received signal. The received signal ri includes a phase error expressed as 290 Δft+θ.
FIG. 2 is a schematic view showing a typical structure of an ordinary frequency/phase synchronization circuit which is included in the demodulation circuit 3 of FIG. 1 and which uses a digital PLL. As shown in FIG. 2, the frequency/phase synchronization circuit is made up of a PLL circuit 11 and a multiplier 12. The PLL circuit 11 is constituted by a multiplier 21, a phase error detector 22, a loop filter 23, and a numerical control oscillator (NCO) 24.
The received signal ri having undergone PSK modulation is input to the multiplier 21 of the PLL circuit 11 and to the multiplier 12. The multiplier 21 of the PLL circuit 11 multiples the received signal ri by a phase control amount e−j(2πΔft+θ) supplied from the numerical control oscillator 24. The signal resulting from the multiplication is output to the phase error detector 22.
The phase error detector 22 detects any phase error that may remain in the signal output from the multiplier 21. The detected phase error is output to the loop filter 23.
For example, if the received signal ri is a signal of a known symbol, the phase error detector 22 detects as the phase error the difference in phase between the symbol of the known symbol and the symbol represented by the output signal coming from the multiplier 21. If the received signal ri is not a signal of a known symbol, then the phase error detector 22 detects as the phase error, the difference in phase between the actual symbol represented by the output signal from the multiplier 21 and the symbol resulting from a hard decision performed by the multiplier 21.
The loop filter 23 is a proportional integral loop filter. As such, the loop filter 23 filters a phase error detection value output from the phase error detector 22 and outputs the filtered result to the numerical control oscillator 24.
More specifically, a multiplier 23-1 of the loop filter 23 multiplies the phase error detection value fed from the phase error detector 22 by a factor of G1 according to a previously established loop gain G1. The result of the multiplication is output to a multiplier 23-2 and an adder 23-4 in the loop filter 23.
The multiplier 23-2 multiplies the G1-fold phase error detection value fed from the multiplier 23-1 by a factor of G2 according to a previously established loop gain G2, and outputs the result of the multiplication to an integrator 23-3. The multipliers 23-1 and 23-2 are each a weighting multiplier that assigns the weight of the loop gain G1 or G2 to the input signal.
The integrator 23-3 integrates the output of the multiplier 23-2, and outputs the integrated result to the adder 23-4. The adder 23-4 adds up the output of the multiplier 23-1 and that of the integrator 23-3. The resulting sum is output as the filtered result to the numerical control oscillator 24.
Based on the filtered result coming from the loop filter 23, the numerical control oscillator 24 generates the phase control amount e−j(2πΔft+θ) and outputs it to the multipliers 21 and 12. The multiplier 12 multiplies the received signal ri by the phase control amount e−j(2πΔft+θ) output from the numerical control oscillator 24. The signal resulting from the multiplication is output as a synchronous detection signal di.
The loop gains G1 and G2 of the loop filter 23 determine the frequency band that is characteristic of the loop filter 23. The frequency band of the loop filter 23 and the performance of the PLL circuit 11 are known to have the following relations therebetween:
The wider the frequency band of the loop filter 23, the higher the capability of the PLL circuit 11 to follow phase error fluctuations and the larger the amount of jitters included in the synchronous detection signal. Conversely, the narrower the frequency band of the loop filter 23, the lower the capability of the PLL circuit 11 to follow phase error fluctuations but the smaller the amount of jitters included in the synchronous detection signal.
Some of the related art is discussed in Japanese Patent Laid-Open No. 2009-26426.